The present invention relates to a data processor and more particularly to its low power consumption mode, for example, an effective art that applies to a data processing system such as a cellular phone that operates by a battery power supply.
A data processor builds in a clock pulse generator that generates a synchronizing clock signal frequency-multiplies and frequency-divides a clock signal formed by a ring oscillator using an oscillator or a clock signal supplied externally, then generates the synchronizing clock signal. A CPU (central processing unit) and an SCI (serial interface circuit) built in the data processor receive the synchronizing clock signal and perform a synchronous operation. A standby mode and a sleep mode are included as low power consumption modes in such data processor. For example, in the standby mode, the operation of a PLL (phase-locked loop) circuit for multiplying a frequency provided in the clock pulse generator or a frequency divider for frequency division is suspended and changes of the synchronizing clock signal inside the data processor are all stopped. In the sleep mode, the input operation of a synchronizing clock input circuit of the CPU is suppressed and the CPU operation is suspended, then the synchronizing clock signal is supplied to another circuit, such as a peripheral circuit, and the circuit can be operated.
For example, there is “Japanese Unexamined Patent Publication No. Hei 3 (1991)-105408 as a document that describes low power consumption modes of electronic equipment. This publication describes an art that controls the supply of a clock signal to a CPU and a peripheral circuit using an oscillation-controlled circuit, and according to a description of the publication, to stop the supply of the clock signal, the connection of clock wiring is disconnected or oscillation itself is stopped.